By Mikhail Kovalev,Silvia M. Müller,Wolfgang J. Paul
This monograph is predicated at the 3rd author's lectures on machine structure, given in the summertime semester 2013 at Saarland college, Germany. It encompasses a gate point building of a multi-core desktop with pipelined MIPS processor cores and a sequentially constant shared memory.
The publication comprises the 1st correctness proofs for either the gate point implementation of a multi-core processor and in addition of a cache established sequentially constant shared reminiscence. This opens how you can the formal verification of synthesizable for multi-core processors within the future.
Constructions are in a gate point version and hence deterministic. against this the reference types opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.
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Additional resources for A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof (Lecture Notes in Computer Science)
A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof (Lecture Notes in Computer Science) by Mikhail Kovalev,Silvia M. Müller,Wolfgang J. Paul